Master 3D Characterization
for Material Science with Tescan Solutions

Common Challenges in High-Resolution Material Analysis

Advanced materials used in energy storage, aerospace, nanotechnology, and biomedical applications require in-depth structural insights. However, traditional imaging techniques often fall short when analyzing multi-phase structures, nanoscale defects, and buried interfaces.

Tescan AMBER X Plasma FIB-SEM addresses these issues by integrating high-throughput Xe+ milling with advanced delayering workflows in a single instrument:

How Sub-20 nm Node Delayering Was Performed Using Tescan AMBER X

A 14 nm Intel Skylake CPU and advanced 7 nm/5 nm CMOS devices were selected to demonstrate precise delayering and in-situ nanoprobing. Initial surface milling was carried out using Xe+ plasma FIB under iFIB+™ control, ensuring layer-by-layer removal across large device areas. Real-time SE signal end pointing was used to identify transistor layers and prevent over-milling.

Nanoflat etch was applied to achieve surface planarity under 5 nm RMS, ensuring reliable probe contact on sensitive low-k dielectrics. A-Maze™ gas chemistry provided selective copper removal while maintaining oxidation-free surfaces.

Following delayering, in-situ nanoprobing was performed directly within the SEM chamber using Kleindiek PS8 probes. Electrical measurements such as EBAC and conductive AFM were integrated into the workflow, enabling transistor-level validation of PMOS and NMOS structures without contamination.

Integrated Delayering and Nanoprobing Reveals Electrical Pathways in Advanced Nodes

A 14 nm Intel Skylake CPU and advanced 7 nm/5 nm CMOS devices were selected to demonstrate precise delayering and in-situ nanoprobing. Initial surface milling was carried out using Xe+ plasma FIB under iFIB+™ control, ensuring layer-by-layer removal across large device areas. Real-time SE signal end pointing was used to identify transistor layers and prevent over-milling.

Nanoflat etch was applied to achieve surface planarity under 5 nm RMS, ensuring reliable probe contact on sensitive low-k dielectrics. A-Maze™ gas chemistry provided selective copper removal while maintaining oxidation-free surfaces.

Following delayering, in-situ nanoprobing was performed directly within the SEM chamber using Kleindiek PS8 probes. Electrical measurements such as EBAC and conductive AFM were integrated into the workflow, enabling transistor-level validation of PMOS and NMOS structures without contamination.

Integrated Delayering and Nanoprobing Reveals Electrical Pathways in Advanced Nodes

A 14 nm Intel Skylake CPU and advanced 7 nm/5 nm CMOS devices were selected to demonstrate precise delayering and in-situ nanoprobing. Initial surface milling was carried out using Xe+ plasma FIB under iFIB+™ control, ensuring layer-by-layer removal across large device areas. Real-time SE signal end pointing was used to identify transistor layers and prevent over-milling.

Nanoflat etch was applied to achieve surface planarity under 5 nm RMS, ensuring reliable probe contact on sensitive low-k dielectrics. A-Maze™ gas chemistry provided selective copper removal while maintaining oxidation-free surfaces.

Following delayering, in-situ nanoprobing was performed directly within the SEM chamber using Kleindiek PS8 probes. Electrical measurements such as EBAC and conductive AFM were integrated into the workflow, enabling transistor-level validation of PMOS and NMOS structures without contamination.

All whitepapers related to this workflow can be easily downloaded as PDFs here: